The virt machine

The board every Warm64 machine is: QEMU's virt layout, its memory map, its devices and its interrupts.

Every Warm64 machine is one board, laid out like QEMU's virt machine. The guest learns about it from a device tree Warm64 builds from the command line; there is no ACPI.

Memory map

AddressDeviceInterrupt
0x0000_0000Two 64 MiB CFI flash banks: the firmware at the reset vector, then its environment
0x0800_0000GIC distributor (GICv2: CPU interface, virtual CPU interface above it)
0x0808_0000GICv3 ITS
0x080a_0000GICv3 redistributors, 0x2_0000 per core
0x0900_0000PL011 UART, the console (ttyAMA0)SPI 1
0x0901_0000PL031 real-time clockSPI 2
0x0902_0000SP805 watchdogSPI 3
0x0903_0000PL061 GPIO: power button, power-off and restart linesSPI 4
0x0904_0000SMMUv3 (with -M virt,iommu=smmuv3)SPI 5, 6
0x0906_0000I2C controller: LM75 temperature sensor, 24C02 EEPROMSPI 7
0x0907_0000PL330 DMA controllerSPI 8
0x0908_0000Second PL011 UART (ttyAMA1)SPI 9
0x0909_0000xHCI USB controller (with -usb or -device wemu-xhci)SPI 10
0x0a00_0000Eight virtio-mmio slotsSPI 16 and up
0x1800_0000Simple framebuffer (ramfb)
0x2000_0000PCI memory window, 256 MiB
0x3000_0000PCIe ECAM configuration space, buses 0 to 15INTx, or MSI-X through the ITS
0x3f00_0000PCI I/O window
0x4000_0000RAM

Interrupts and timers

  • GICv3 by default, with an ITS for PCIe MSI-X; GICv2 with -M virt,gic-version=2, where PCI devices use INTx.
  • The Arm generic timers, per core, at 62.5 MHz, keeping time with the host's clock.

Boot

  • -kernel loads a Linux Image into RAM and starts it with the device tree, the way a bootloader would.
  • -bios and -pflash put firmware in the first flash bank, where the cores start.
  • There's no EL3 firmware: Warm64 answers PSCI calls itself, to start, stop and reset cores.

Virtio devices

Disks, network cards, shared folders, the GPU, input and sound are virtio devices. On virtio-mmio (the default) the machine has eight slots for them in all. Naming any device with -pci moves every virtio device behind the PCIe host bridge instead; see PCI or MMIO.

See also