CPU
The Arm64 core every Warm64 machine runs: the instruction sets it implements, the features it advertises, and its exception levels.
Every core is a Cortex-A76 (r4p1, MIDR 0x414fd0b1) that implements the complete A64 instruction set. The -cpu model decides only which optional features the guest is told about; see CPU models.
Instruction sets
| Area | Implemented |
|---|---|
| Integer | The complete A64 integer set, LSE and 128-bit atomics, CRC32, FlagM, LRCPC, JSCVT, the MOPS memory copy and set instructions, CSSC, LS64 |
| Floating point | Half, single and double precision, with all four rounding modes, flush-to-zero, default NaN, NaN propagation order and every FPSR flag |
| Advanced SIMD | The full vector and scalar set, with FP16, RDM, DotProd, FHM, FCMA, BF16 and I8MM |
| Crypto | AES, SHA-1, SHA-256, SHA-512, SHA-3, SM3, SM4, and 64-bit polynomial multiply |
| Scalable vectors | SVE and SVE2 at vector lengths from 128 to 2048 bits; SME and SME2 with the ZA array |
| Security | Pointer authentication (QARMA5, all five keys), BTI, MTE2 with synchronous and asynchronous faults |
| 32-bit | A32 and T32 (Thumb) code in AArch32 state, IT blocks included |
| Debug | Self-hosted debug (breakpoints, watchpoints, software step), and a PMUv3 with a cycle counter and four event counters |
What the guest is told
| Model | Advertised |
|---|---|
| Any model | The base A64 set, Advanced SIMD with its extensions, the crypto extension, LSE atomics, CRC32, BTI |
-cpu max | All of the above, plus pointer authentication, MTE and SVE |
SME and AArch32 at EL0 are implemented but never advertised. With -cpu max, Linux reports:
fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 asimdfhm ilrcpc flagm sb sve paca pacg dcpodp flagm2 frint i8mm bf16 bti mteException levels
- EL0 to EL3, each with its own translation regime.
- EL2 with the Virtualization Host Extensions and stage-2 translation. Linux boots at EL2 by default;
-M virt,virtualization=offboots it at EL1. - EL3, the secure monitor, is implemented; with no EL3 firmware, Warm64 answers PSCI calls itself.
Memory management
The VMSAv8-64 MMU with 4K, 16K and 64K granules, hardware access-flag and dirty-bit management, PAN and UAO, and TLB maintenance broadcast across cores.